Whether you’re designing circuits for a new IC or for a PCB layout with discrete components, coupling capacitance will exist between groups of conductors in your design. You can never truly eliminate parasitics like DC resistance, copper roughness, mutual inductance, and mutual capacitance. However, with the right design choices, you can reduce these effects to the point that they do not cause excess crosstalk or signal distortion.
Coupling inductance is quite easy to spot as it arises in two principle ways:
1.Two nets that are not running perpendicular and are referenced back to a ground plane can have loops that face each other (mutual inductance).
2.Every plane that provides a return current path will have some coupling inductance with its reference nets (self-inductance).
Coupling capacitance can be more difficult to pinpoint as it occurs everywhere. Anytime conductors are placed in a PCB or IC layout, they will have some capacitance. A potential difference between these two conductors causes them to charge and discharge like a typical capacitor. This causes displacement currents to divert away from load components and signals to crossover between nets at high frequency (i.e., crosstalk).
With the right set of circuit simulator tools, you can model how coupling capacitance in an LTI circuit affects signal behavior in the time domain and frequency domain. Once you design your layout, you can extract the coupling capacitance from impedance and propagation delay measurements. By comparing the results, you can determine if any layout changes are required to prevent unwanted signal coupling between nets.
Tools for Modeling Coupling Capacitance
Because the coupling capacitance in your layout is unknown until the layout is completed, the place to start modeling coupling capacitance is in your schematic. This is done by adding a capacitor at strategic locations to model specific coupling effects in your components. This allows phenomenological modeling of coupling capacitance depending on where the capacitor is placed:
Input/output capacitance. The input and output pins in a real circuit (ICs) will have some capacitance due to separation between the pin and the ground plane. These capacitance values are usually ~10 pF for small SMD components. This is one of the primary points to be examined in a pre-layout simulation.
Capacitance between nets. Placing a capacitor between two nets that carry input signals will model crosstalk between the nets. By visualizing the victim and aggressor net, you can see how switching on the aggressor induces a signal on the victim. Because these capacitances are quite small and crosstalk also depends on mutual inductance, crosstalk simulations are normally only performed post-layout for the highest accuracy.
Trace capacitance back to a ground plane. Even if a trace is short, it will still have parasitic capacitance with respect to the ground plane, which is responsible for resonance on short transmission lines.